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AT24C128B
cycles, (c) create another start bit followed by stop bit condition as shown below. The device is
ready for next communication after above steps have been completed.
Figure 6-3.
Software Reset
Start bit
Dummy Clock Cycles
Start bit
Stop bit
SCL
1
2
3
8
9
SDA
Figure 6-4.
Bus Timing
t F
t HIGH
t R
SCL
t LOW
t LOW
t SU.STA
t HD.STA
t HD.DAT
t SU.DAT
t SU.STO
SDA IN
Figure 6-5.
SCL
SDA OUT
Write Cycle Timing
t AA
t DH
t BUF
SDA
8th BIT
ACK
WORDn
(1)
t wr
STOP
CONDITION
START
CONDITION
Note:
1. The write cycle time t WR is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle.
7
5296A–SEEPR–1/08
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功能描述:电可擦除可编程只读存储器 SERIAL 电可擦除可编程只读存储器 128K (16K x 8) 2WIRE 1.7V RoHS:否 制造商:Atmel 存储容量:2 Kbit 组织:256 B x 8 数据保留:100 yr 最大时钟频率:1000 KHz 最大工作电流:6 uA 工作电源电压:1.7 V to 5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-8
